1. Field of the Invention
The present invention generally relates to high performance field effect transistors suitable for extremely high density semiconductor integrated circuits and, more particularly, to dual gate field effect transistors having the source and drain located one above the other and other semiconductor devices having borderless contacts.
2. Description of the Prior Art
Field effect transistors have been known for a number of years and are now the transistor of choice for use in complex integrated digital circuit for all but the most stringent of high frequency requirements. In general, field effect transistors can be fabricated somewhat more simply and with larger process windows than bipolar transistors and, additionally, allow simplified circuit and device design.
As demands for higher digital switching performance have increased, as well as demands for increased functionality and economy of manufacture, constraints on transistor footprint size (and, hence, current-carrying capacity) have also increased. Further, to reduce power dissipation requirements as more transistors are placed within a given chip space and switching and/or clock frequencies are increased, operation at decreased voltages has been required. Operation at reduced voltage tends to reduce operating margins and the difference in resistance between the on and off states of the transistor. This effect is due to the reduced ability to control depletion at greater distances from the gate dielectric within the conduction channel with reduced voltages.
Therefore, there has been recent interest in field effect transistor designs which include gate electrodes on opposite sides of or fully or partially surrounding the conduction channel. Further, from the standpoints of both performance and circuit design and functionality, it has been found to be very desirable to provide for different voltages to be applied to separated gate structures on opposite sides of the conduction channel.
However, providing one or more gate structures on opposing surfaces of the conduction channel or even a single gate structure extending on different sides of the conduction channel implies increased structural complexity of the transistor. This increased complexity cannot always be achieved at sizes the same as or smaller than conventional field effect transistors. For example, several successful designs have been recently achieved using a vertical fin as a conduction channel with gate structures disposed on the lateral sides thereof. However, the conduction path is substantially parallel to the chip surface and, while the designs allow some structures to be formed at sub-lithographic sizes (e.g. smaller than the resolution of the lithography tool used for resist patterning exposures to form other structures), the source and drain must be physically separated from the gate structure; increasing at least one dimension of the transistor footprint.
Additionally, some lithographic techniques to increase resolution of radiant energy lithography tools, such as phase-shift masks, can only form features of closed geometric shape. This limitation often requires an additional xe2x80x9ctrimmingxe2x80x9d process to establish, for example, channel length of transistors and generally compromises the ability to maintain tight control thereof.
Further, due to the basic nature of lithography and semiconductor processes, it has been an almost universal practice to configure field effect transistors such that the conduction channel extends substantially parallel to the chip surface. While field effect transistors could, in theory, be configured to have the conduction channel extend substantially perpendicular to the chip surface (e.g. xe2x80x9cverticallyxe2x80x9d), as a practical matter, at least the formation of connections to the source, drain and gate of the transistor are made much more difficult in designs proposed to date; reducing manufacturing yield and consuming substantial chip space as well as greatly increasing process complexity.
It is therefore an object of the present invention to provide a field effect transistor having dual and potentially independent gate structures of reduced footprint and which can be reliably formed at high integration density by providing a vertically extending conduction channel.
It is another object of the invention to provide a dual gate vertical field effect transistor which can be reliably formed at small size and high integration density by different lithographic techniques.
It is a further object of the invention to provide a vertical field effect transistor design allowing contacts to be conveniently made to the source, gate and drain thereof whereby the contact to the lower diffusion is borderless to the gate.
In order to accomplish these and other objects of the invention, a vertical field effect transistor is provided including a semiconductor pillar conduction channel, gate electrodes in trenches adjacent the semiconductor pillar, a layer of insulator adjacent the gate electrodes and opposite the semiconductor pillar, sidewalls adjacent the semiconductor pillar above the gate electrodes in the trenches, insulator material in the trenches above the gate electrodes and adjacent the sidewalls, the insulator material being selectively etchable relative to the sidewalls and the semiconductor pillar.
In accordance with another aspect of the invention, an integrated circuit device is provided including isolation material surrounding transistor locations in a substrate, vertical field effect transistors formed at the transistor locations and having a gate electrode structure formed in a trench, a layer of insulator material in the trench between the isolation material and the gate electrode structure, the isolation material being selectively etchable relative to the layer of insulator material and a contact opening formed along an interface of the insulator layer and the isolation material.
In accordance with a further aspect of the invention, a method of making a semiconductor device including a field effect transistor is provided including steps of forming a semiconductor pillar in a trench in a body of a first insulating material, the trench extending to a layer of semiconductor material, forming a layer of a second insulating material on walls of the trench, and etching a contact opening to the semiconductor material through the first insulating material selectively and adjacent to the second insulating material.
In accordance with yet another aspect of the invention, a transistor is provided comprising a substrate, a first diffusion, a second diffusion above the first diffusion, a channel extending vertically between the first diffusion and the second diffusion, a gate structure extending on at least one side of the channel, and a contact to the first diffusion borderless to said gate structure.